1. Field of the Invention
The present invention relates to a light emitting display, and more particularly, to a light emitting display having decreased parasitic capacitance.
2. Discussion of the Background
Various flat panel displays have been recently developed to replace the heavier and bulkier cathode ray tube (CRT). Such displays include the liquid crystal display (LCD), field emission display (FED), plasma display panel (PDP), light emitting display (LED), etc.
Among flat panel displays, the self-emissive light emitting display utilizes electron-hole recombination in a fluorescent layer to emit light. Such a light emitting display has a relatively fast response time, and it consumes relatively less power.
Referring to FIG. 1, a light emitting display may comprise a plurality of pixels 10 that receive a data signal from a data line Dn in response to a selection signal of a scan line Sm and emit light corresponding to the received data signal.
Here, each pixel 10 may include an organic light emitting device OLED, the data line Dn, the scan line Sm, and a pixel circuit 12 connected to an anode of the organic light emitting device OLED.
The organic light emitting device OLED may include the anode, an emitting layer formed on the anode, and a cathode formed on the emitting layer. The anode is connected to the pixel circuit 12, and the cathode may be connected to a second power line VSS. The emitting layer, which comprises at least a light emitting layer, may also include an electron transport layer interposed between the emitting layer and the cathode and a hole transport layer interposed between the emitting layer the anode. Additionally, the organic light emitting display OLED may comprise an electron injection layer and a hole injection layer. In such an organic light emitting display OLED, applying a voltage between the anode and the cathode generates electrons from the cathode, which move to the emitting layer via the electron injection layer and the electron transport layer, and holes from the anode, which move to the emitting layer via the hole injection layer and the hole transport layer. The electrons and holes then recombine in the emitting layer, thereby causing light to be emitted.
The pixel circuit 12 comprises a driving thin film transistor (TFT) MD connected between the first power line VDD and the organic light emitting device OLED, a switching TFT MS connected to the driving TFT MD, the data line Dn and the scan line Sm, and a storage capacitor Cst connected between gate and source electrodes of the driving TFT MD. Here, the driving TFT MD and the switching TFT MS are shown as P-type metal oxide semiconductor field effect transistors (MOSFET).
The switching TFT MS comprises a gate electrode connected to the scan line Sm, a source electrode connected to the data line Dn, and a drain electrode connected to a first terminal of the storage capacitor Cst. Here, the switching TFT MS turns on in response to the selection signal of the scan line Sm, and supplies the data signal from the data line Dn to the storage capacitor Cst, which stores a voltage corresponding to the supplied data signal.
The driving TFT MD comprises the gate electrode connected to the first terminal of the storage capacitor Cst, the source electrode connected to a second terminal of the storage capacitor Cst and the first power line VDD, and a drain electrode connected to the anode of the organic light emitting device OLED. Here, the driving TFT MD supplies a current to the organic light emitting device OLED corresponding to the voltage stored in the storage capacitor Cst, and the organic light emitting device OLED emits light corresponding to the current supplied from the driving TFT MD.
However, in such a conventional light emitting display, parasitic capacitors CP1 and CP2 of each pixel 10 may cause decreased picture quality. Referring to FIG. 1 and FIG. 2, in the pixel 10 connected to the nth data line Dn (where n is a natural number), the first parasitic capacitor CP1 is formed between the storage capacitor Cst and the nth data line Dn, and the second parasitic capacitor CP2 is formed between the anode of the organic light emitting device OLED and the nth data line Dn.
Hence, in the pixel 10 connected to the nth data line Dn, the first parasitic capacitor CP1 and the second parasitic capacitor CP2 are connected to the nth data line Dn. Thus, when a data signal is supplied to the data line Dn in response to the selection signal, the first and second parasitic capacitors CP1 and CP2 may vary the voltage applied to the pixel 10, thereby deteriorating picture quality. Particularly, to secure a sufficient aperture ratio, the anode and the data line Dn, and the storage capacitor Cst and the data line Dn, are formed as close as possible (refer to FIG. 2), respectively. However, the closer these elements are formed, the more the capacity of the first and second parasitic capacitors CP1 and CP2 increases, thereby further deteriorating picture quality.
Additionally, in the pixel 10 of FIG. 1, the TFTs may have different threshold voltages Vth, which increases the difficulties in representing high gradation. A light emitting display, such as that shown in FIG. 3, has been proposed to solve this problem.
Referring to the light emitting display of FIG. 3, a pixel 20 is selected when the selection signal is applied to the scan line Sm, and it emits light corresponding to the data signal applied to the data line Dn.
Each pixel 20 may include the organic light emitting device OLED, and a pixel circuit 22 that drives the organic light emitting device OLED to emit light. The pixel circuit 22 is connected to the data line Dn, the scan line Sm and an emitting control line EMIm.
The organic light emitting device OLED may include an anode connected to the pixel circuit 22, and the cathode connected to a second power line VSS. Here, the organic light emitting device OLED emits light corresponding to the current supplied from the pixel circuit 22.
The pixel circuit 22 comprises the driving TFT MD connected between the first power line VDD and the organic light emitting device OLED; the emitting control line EMIm; a fourth switching device MS4 connected to the organic light emitting device OLED and the driving TFT MD; a first switching device MS1 connected to the mth scan line Sm and the nth data line Dn; a second switching device MS2 connected to the first switching device MS1, the first power line VDD and the (m−1)th scan line Sm−1; a third switching device MS3 connected to a first node N1 between the driving TFT MD and the fourth switching device MS4, the (m−1)th scan line Sm−1, and the gate electrode of the driving TFT MD; the storage capacitor Cst connected to a second node N2 between the first and second switching devices MS1 and MS2, and the first power line VDD; and a compensation capacitor Cvth connected between the second node N2 and the driving TFT MD. Here, the driving TFT MD and the switching transistors MS1, MS2, MS3 and MS4 are shown as P-type MOSFETs.
The pixel 20 may be driven as follows. Referring to FIG. 4, for a period of T1, a low selection signal SS is supplied to the (m−1)th scan line Sm−1 while supplying a high level signal to the mth scan line Sm. Further, a high light emission signal EMI is supplied to the emitting control line EMIm. When supplying the low selection signal SS to the (m−1)th scan line Sm−1, the second and third switching devices MS2 and MS3 are turned on. When supplying the high level signal to the mth scan line Sm, the first switching device MS1 is turned off, and when supplying the high light emission signal EMI to the emitting control line EMIm, the fourth switching device MS4 is turned off.
For the period of T1, in which the second and third switching devices MS2 and MS3 are turned on, the driving TFT MD functions as a diode, and a voltage applied between the gate and source electrodes of the driving TFT MD varies until it reaches the threshold voltage of the driving TFT MD. Accordingly, the compensation capacitor Cvth stores a compensation voltage corresponding to the threshold voltage Vth of the driving TFT MD.
For a period of T2, the high level signal is supplied to the (m−1)th scan line Sm−1, and the low selection signal SS is supplied to the mth scan line Sm. Further, the high light emission signal EMI is supplied to the emitting control line EMIm. When supplying the high level signal to the (M−1)th scan line Sm−1, the second and third switching devices MS2 and MS3 are turned off. When supplying the low selection signal SS to the mth scan line Sm, the first switching device MS1 is turned on. When supplying the high light emission signal EMI to the emitting control line EMIm, the fourth switching device MS4 remains turned off.
For the period of T2, in which the first switching device MS1 is turned on, the data signal may be supplied from the data line Dn to the second node N2 through the first switching device MS1, thereby charging the storage capacitor Cst with a voltage corresponding to the data signal. At this time, the gate electrode of the driving TFT MD is supplied with the sum of the voltage (i.e. Vdata-VDD) charged in the storage capacitor Cst and the compensation voltage charged in the compensation capacitor Cvth. That is, in the light emitting display of FIG. 3, the compensation capacitor Cvth is charged with the voltage corresponding to the threshold voltage Vth of the driving TFT MD, thereby compensating for the driving transistor's threshold voltage Vth. Therefore, the brightness may be made more uniform regardless of positions of the pixel 20.
Further, in the conventional light emitting display of FIG. 3, the equivalent parasitic capacitors CP1 and CP2 formed in each pixel 20 may still decrease picture quality. Referring to FIG. 3, in the pixel 20 connected to the nth data line Dn, the first parasitic capacitor CP1 is formed between the storage capacitor Cst and the nth data line Dn, and the second parasitic capacitor CP2 is formed between the anode of the organic light emitting device OLED and the nth data line Dn.
Hence, in the pixel 20 connected to the nth data line Dn, the first and second parasitic capacitors CP1 and CP2 are connected to the nth data line Dn. Thus, when a data signal is supplied to the data line Dn in response to the selection signal, the first and second parasitic capacitors CP1 and CP2 may vary the voltage applied to the pixel 20, thereby deteriorating picture quality. Further, because the first and second parasitic capacitors CP1 and CP2 of FIG. 1 or FIG. 3 may have one tenth or more of the capacity of the storage capacitor Cst, a large variation may occur in the voltage applied to the pixels 10 and 20, as FIG. 5 and FIG. 6 show.